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W25Z040A 128k 36 pipelined zws sram publication release date: april 1999 - 1 - revision a2 general description the W25Z040A is a high-speed, low-power, zero-wait-state (zws) synchronous pipelined cmos static ram organized as 131,072 36 bits. a built-in two-bit burst address counter supports both linear and interleaved burst mode. the mode to be executed is controlled by the lbo pin. a snooze mode can reduce the power dissipation. the zws sram is optimized for 100 percent bus utilization by eliminating wait states when transitioning from read to write, or vice versa. all addresses, data inputs, clock enable ( clke ), write enable ( we ), byte-write enables ( bw [4:1]) and chip enables ( ce1 , ce2 and ce3 for easy depth expansion) are synchronously sampled with by a positive-edge-triggered clock (clk). asynchronous inputs include the output enable ( oe ), clock (clk) and snooze (zz). to provide 100 percent use of the data bus, the pipelined zws sram uses the two-stage write address registers. for example, when the address and control signals are applied to the sram in clock cycle one, the data associated with the address occurs two cycles later, or the clock cycle three. the W25Z040A operates on a single 3.3v power supply, with all inputs and outputs compatible with the lvttl interface. based on the bus efficiency, the device is ideal for high bandwidth application systems. features synchronous operation high-speed access time: 3.8/4.2/4.5/5 ns single +3.3v power supply individual byte write capability 3.3v lvttl compatible i/o clock-controlled and registered input asynchronous output enable zero wait states between read/write cycles supports snooze mode (low-power state) internal burst counter supports interleaved b urst mode & linear burst mode packaged in 100-pin tqfp block diagram a0 : a16 add reg burst counter write add reg #0 128k x 36 core cell write data reg #1 lbo k1 a0, a1 mux mux write data reg #0 output reg write add reg #1 output buffer k k k read/write control k k k1 clk oe adv/ld, we, bw[4:1] clke ce1 ce2 ce3 i/o[36:1] ?
W25Z040A - 2 - pin configuration 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 80 79 78 77 76 75 74 73 72 71 70 69 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 8 1 8 2 8 3 8 4 8 5 8 6 8 7 8 8 8 9 9 0 9 1 9 2 9 3 9 4 9 5 9 6 9 7 9 8 9 9 1 0 0 / i/o18 i/o17 i/o16 vddq vssq i/o15 i/o14 i/o13 i/o12 vssq vddq i/o11 i/o10 vss vdd zz i/o9 i/o8 vddq vssq i/o7 i/o6 i/o5 i/o4 vssq vddq i/o3 i/o2 i/o19 i/o20 i/o21 vddq vssq i/o22 i/o23 i/o24 i/o25 vssq vddq i/o26 i/o27 /ft vdd vss i/o28 i/o29 vddq vssq i/o30 i/o31 i/o32 i/o33 vssq vddq i/o34 i/o35 / l b o a 5 a 4 a 3 a 2 a 1 a 0 r s v v s s v d d a 1 0 a 1 1 a 1 2 a 1 3 a 1 4 100-pin tqfp mo-136 a 1 5 vdd vdd r s v r s v r s v a 1 6 i/o1 i/o36 a d a 6 a 7 / c e 1 c e 2 / b w 4 / b w 3 / b w 2 / b w 1 / c e 3 v d d v s s / o e / l d a 8 a 9 n c v n c c l k c k / w e e l
W25Z040A publication release date: april 1999 - 3 - revision a2 pin description symbol type description a0 - a16 input, synchronous host address i/o1 - i/o36 i/o, synchronous data inputs/outputs clk input, clock processor host bus clock clke input, synchronous clock enable ce1 , ce2, ce3 input, synchronous chip enables we input, synchronous write enable from system controller bw1 - bw4 input, synchronous host bus byte enables used with we oe input, asynchronous output enable input adv/ ld input, synchronous internal burst address counter advance(sampled high) / load external address (sampled low) zz input, asynchronous snooze pin for low-power state, internally pulled low ft input, static this pin should be connected to v dd or unconnected to meet the specification in pipelined mode operation. lbo input, static lower address burst order connected to v ss : device operates in linear mode. connected to v dd or unconnected: device is in non- linear mode. v ddq i/o power supply v ssq i/o ground v dd power supply v ss ground rsv reserved pin, don't use these pins nc no connection
W25Z040A - 4 - functional description read operation the address is registered on the rising edge of clk and the associated output data will be valid after two cycles later. write operation during the write operation, the input data follows the address by two cycles later. the new incoming address and data are transferred into a two-stage write buffer while the residing address which are received two write cycles earlier are used for actual write operation. data stored in these two-stage write data registers are used for first two write cycles following the read or unselected cycle. a subsequent read which matches the address in either write buffer allows the corresponding buffer data to be passed directly to output register. truth table cycle address used zz ce1 ce2 ce3 clke adv/ ld we bwx data notes unselected no 0 1 x x 0 0 x x hi-z unselected no 0 x 0 x 0 0 x x hi-z unselected no 0 x x 1 0 0 x x hi-z begin read external 0 0 1 0 0 0 1 x d-out 3 continue read next 0 x x x 0 1 x x d-out 3 begin write external 0 0 1 0 0 0 0 0 d-in begin write /nop none 0 0 1 0 0 0 0 1 hi-z 4 continue write next 0 x x x 0 1 x 0 d-in continue write /nop next 0 x x x 0 1 x 1 hi-z 4 stall current 0 x x x 1 x x x - 5 snooze none 1 x x x x x x x hi-z notes: 1. for a detailed definition of read/write, see the write table below. 2. an "x" means don't care, "1" means logic high, and "0" means logic low. 3. the oe pin enables the data output and is not sampled with the clock. all signals of the sram are sampled synchronously with the bus clock except for the oe pin. 4. nop can be seen as no operation. 5. if clock enable sampled high occurs during read cycle, the bus will remain active (valid data). if clock enable sampled high occurs during write cycle the bus will remain in high-z state.
W25Z040A publication release date: april 1999 - 5 - revision a2 write table read/write function we bw4 bw3 bw2 bw1 read 1 x x x x write/nop 0 1 1 1 1 write byte 1 i/o1 - i/o9 0 1 1 1 0 write byte 2 i/o10 - i/o18 0 1 1 0 1 write byte 2, byte 1 0 1 1 0 0 write byte 3 i/o19 - i/o27 0 1 0 1 1 write byte 3, byte 1 0 1 0 1 0 write byte 3, byte 2 0 1 0 0 1 write byte 3, byte 2, byte 1 0 1 0 0 0 write byte 4 i/o28 - i/o36 0 0 1 1 1 write byte 4, byte 1 0 0 1 1 0 write byte 4, byte 2 0 0 1 0 1 write byte 4, byte 2, byte 1 0 0 1 0 0 write byte 4, byte 3 0 0 0 1 1 write byte 4, byte 3, byte 1 0 0 0 1 0 write byte 4, byte 3, byte 2 0 0 0 0 1 write all bytes i/o1 - i/o36 0 0 0 0 0 read-write-read operation there is no wait state to be asserted for a read-write-read operation. i.e. there is no extra dead bus cycle for read-write or write-read recovering and the bus utilization is 100%.
W25Z040A - 6 - burst mode operation burst read or write is activated if adv/ ld = high at the rising edge of clk, where the new address is composed of 2 new bits from burst counter and the remaining bits from the previous address. the sequencing of the counter can be either linear if lbo = low or interleaved if lbo = high. ce [3:1] and we controls are ignored during burst mode. burst address sequence interleaved mode ( lbo = v dd ) linear mode ( lbo = v ss ) a[1:0] a[1:0] a[1:0] a[1:0] a[1:0] a[1:0] a[1:0] a[1:0] external start address 00 01 10 11 00 01 10 11 second address 01 00 11 10 01 10 11 00 third address 10 11 00 01 10 11 00 01 fourth address 11 10 01 00 11 00 01 10 stall cycle stall cycle occurs when clke = high is sampled. no internal clocks are generated. all addresses and control signals are ignored. if the previous cycle is a read, output remains the same. if the previous cycle is a write, output remains tri-stated. any stall cycle will be added to increase the latency of output and input data. unselect cycle when ce = high is sampled, a unselect state is entered. output is tri-stated. by setting adv/ ld = high for the following sampling cycle, the unselect state can be continued. nop cycle for a write cycle with no asserted byte-write select signal, the device achieves a nop operation. no addresses will be sampled. power down mode an asynchronous zz pin can be set high to force the device into a power down mode. outputs will go into high-z state and the device draws only standby power. minimum of 2 clk cycles are required after setting zz to high before the device is forced into power down operation. any operation pending when entering power down mode (read or write) is not guaranteed to successfully complete. therefore, zz mode must not be initiated until valid pending operations are completed. when exiting zz mode during t zzr , only the unselect or read cycle should be given while the sram will be waken up again.
W25Z040A publication release date: april 1999 - 7 - revision a2 absolute maximum ratings parameter rating unit core supply voltage to vss -0.5 to 4.6 v i/o supply voltage to vss -0.5 to 4.6 v input/output to v ssq potential v ssq -0.5 to v ddq +0.5 v allowable power dissipation 1.5 w storage temperature -65 to 150 c operating temperature 0 to +70 c note: exposure to conditions beyond those listed under absolute maximum ratings may adversely affect the life and reliability of the device. operating characteristics (v dd /v ddq = 3.3v 5%, v ss / v ssq = 0v, t a = 0 to 70 c) parameter sym. test conditions min. typ. max. unit input low voltage v il - -0.5 - +0.8 v input high voltage v ih - +2.0 - v dd +0.3 v input leakage current i li v in = v ssq to v ddq -1 - +1 m a output leakage current i lo v i/o = v ssq to v ddq, and data i/o pins in high-z state defined in truth table -1 - +1 m a output low voltage v ol i ol = +8.0 ma - - 0.4 v output high voltage v oh i oh = -4.0 ma 2.4 - - v operating current i dd all inputs 3 v ih or v il, -3a - - 420 ma t cyc 3 min., i/o = 0 ma -4 - - 370 ma -4a - - 330 ma -5 - - 300 ma standby current i sb1 device unselected, zz v ss + 0.2, all inputs v ss + 0.2 or 3 v dd -0.2, and static i/o = 0 ma , clk frequency = 0 - - 10 ma standby current i sb2 device unselected, zz = v il , all inputs v il or 3 v ih , i/o = 0 ma, clk frequency = 0 - - 25 ma zz mode current i zz zz 3 v ih , all inputs v il or 3 v ih , i/o = 0 ma - - 10 ma note: typical characteristics are measured at v dd = 3.3v, t a = 25 c.
W25Z040A - 8 - capacitance (v dd = 3.3v, t a = 25 c, freq. = 1 mhz) parameter sym. conditions max. unit address input capacitance c add v in = 0v 3.5 pf clock & control input capacitance c clk v clk = 0v 4 pf input/output capacitance c i/o v i/o = 0v 5 pf note: these parameters are sampled but not 100% tested. ac test conditions parameter conditions input pulse levels 0v to 3v input rise and fall times 1 ns input and output timing reference level 1.5v output load c l = 30 pf, i oh /i ol = -4 ma/8 ma ac test loads and waveform 90% 90% 1.0 ns 10% 1.0 ns 10% rl = 50 ohm vl = 1.5v output 5 pf r2 350 ohm r1 320 ohm 3.3v output 30 pf including jig and scope 3.0v 0v including jig and scope zo = 50 ohm (for t khz, t klz, t ohz, t olz, measurement)
W25Z040A publication release date: april 1999 - 9 - revision a2 ac timing characteristics (v dd /v ddq = 3.3v 5%, v ss /v ssq = 0v, t a = 0 to 70 c, all timings measured in pipelined mode) parameter sym. W25Z040A -3a W25Z040A -4 W25Z040A -4a W25Z040A -5 unit notes min. max. min. max. min. max. min. max. clock cycle time t cyc 6.7 - 7.5 - 8.5 - 10.0 - ns clock high pulse width t kh 2.5 - 3.0 - 3.0 - 3.5 - ns clock low pulse width t kl 2.5 - 3.0 - 3.0 - 3.5 - ns input setup time t s 1.5 - 1.5 - 2.0 - 2.0 - ns input hold time t h 0.5 - 0.5 - 0.5 - 0.5 - ns clock access time t kq - 3.8 - 4.2 - 4.5 - 5.0 ns output hold from clock high t kx 1.5 - 1.5 - 1.5 - 1.5 - ns clock high to output low-z t klz 1.5 - 1.5 - 1.5 - 1.5 - ns 1 clock high to output high-z t khz - 3.0 - 3.5 - 3.5 - 3.5 ns 1 output enable to output valid t oe - 3.8 - 4.2 - 4.5 - 5.0 ns output enable to output low-z t olz 0 0 0 0 ns 1 output disable to output high-z t ohz - 3.0 - 3.5 - 3.5 - 3.5 ns 1 zz standby time t zzs - 2 - 2 - 2 - 2 cycle zz recover time t zzr - 20 - 20 - 20 - 20 ns 4 notes: 1. these parameters are sampled but not 100% tested. 2. in the zz mode, the sram will enter a low-power state. in this mode, data retention is guaranteed and the clock is active. 3. configuration signals lbo and ft are static and should not be changed during operation. 4. write cycle should not be given for at least 20 ns while the sram is transitioning out of zz mode.
W25Z040A - 10 - timing waveforms read/write cycle timing n clk a[16:0] read write write read read read write n+1 n+2 n+3 n+4 n+5 n+6 clke we bw[4:1] ce[3:1] i/o[36:1] dn+2 dn+3 qn+4 dn+5 qn qn+1 kq t kx t t s h t t s h t t kh kl t oe olz t klz t khz t oe t ohz t t s h t t s h t t s h t t s h t
W25Z040A publication release date: april 1999 - 11 - revision a2 timing waveforms, continued burst read/write cycle timing n burst read burst read write burst write read read burst write m p clk a[16:0] clke we bw[4:1] ce[3:1] adv/ld dm dm+1 qn qn+1 qn+2 dm+2 i/o[36:1] oe t kh kl t t s h t olz t oe t kq t kx t ohz t khz t t s h t
W25Z040A - 12 - timing waveforms, continued stall nop and unselect cycle timing 1 n clk add[16:0] stall write stall read read nop deselect continued deselect write n+1 n+2 n+3 clke we bw[4:1] adv/ld ce[3:1] i/o[36:1] dn+1 dn+3 qn qn+2 oe t s h t oe t ohz t t s h t kq t
W25Z040A publication release date: april 1999 - 13 - revision a2 timing waveforms, continued stall nop and unselect cycle timing 2 n stall write stall read read deselect continued deselect n+1 n+2 n+3 read n+4 clk add[16:0] clke we bw[4:1] adv/ld ce[3:1] i/o[36:1] dn+1 dn+3 qn qn+2 oe write t s h t oe t t s h t kq t
W25Z040A - 14 - ordering information part no. access time ( n s) operating current max. ( m a) standby current max. ( m a) package W25Z040Ad-3a 3.8 420 25 100-pin tqfp W25Z040Ad-4 4.2 370 25 100-pin tqfp W25Z040Ad-4a 4.5 330 25 100-pin tqfp W25Z040Ad-5 5.0 300 25 100-pin tqfp notes: 1. winbond reserves the right to make changes to its products without prior notice. 2. purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure.
W25Z040A publication release date: april 1999 - 15 - revision a2 package dimensions 100-pin tqfp e h e y a a seating plane l l 1 see detail f h d d 2 1 b e c 1. dimensions d & e do not include interlead flash. 2. dimension b does not include dambar protrusion/intrusion. 3. controlling dimension: millimeters 4. general appearance spec. should be based on final visual inspection spec. 0.08 0 7 0 0.003 1.00 0.75 16.10 0.60 16.00 0.45 15.90 0.039 0.030 0.870 0.634 0.024 0.866 0.630 0.018 0.862 0.626 0.65 20.10 14.10 0.20 0.38 1.45 20.00 14.00 1.40 19.90 13.90 0.10 0.22 1035 0.791 0.555 0.008 0.015 0.057 0.787 0.551 0.055 0.026 0.783 0.547 0.004 0.009 0.053 notes: symbol min. nom. max. max. nom. min. dimension in inches dimension in mm e h d h e l y q l 1 a b c d a a 1 2 e 0.013 0.006 0.15 0.32 21.90 22.00 22.10 7 0.020 0.032 0.498 0.802 0.10 0.05 0.002 0.004 0.006 0.15
W25Z040A - 16 - version history version date page description a1 mar. 1998 initial issued a2 apr. 1999 1, 4, 6, 7, 9, 14 change speed bin from 133 to 150 mhz cancel packaged in 100-pin qfp 3 dc functional pins ( lbo , ft ) connect to v ss or v dd 10~13 marks the detail specifications in the waveforms headquarters no. 4, creation rd. iii, science-based industrial park, hsinchu, taiwan tel: 886-3-5770066 fax: 886-3-5796096 http://www.winbond.com.tw/ voice & fax-on-demand: 886-2-27197006 taipei office 11f, no. 115, sec. 3, min-sheng east rd., taipei, taiwan tel: 886-2-27190505 fax: 886-2-27197502 winbond electronics (h.k.) ltd. rm. 803, world trade square, tower ii, 123 hoi bun rd., kwun tong, kowloon, hong kong tel: 852-27513100 fax: 852-27552064 winbond electronics north america corp. winbond memory lab. winbond microelectronics corp. winbond systems lab. 2727 n. first street, san jose, ca 95134, u.s.a. tel: 408-9436666 fax: 408-5441798 note: all data and specifications are subject to change without notice.

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